Every artificial intelligence model that matters runs on chips manufactured by one company, on one island, in the most geopolitically contested strait on Earth. Taiwan Semiconductor Manufacturing Company controls approximately 70% of the global foundry market and over 90% of the world’s most advanced chips below 7nm. Its 2026 capital expenditure of $52–56 billion exceeds the GDP of most nations. Its CoWoS advanced packaging — the process that bonds AI processors to high-bandwidth memory — is sold out through 2027 with demand running at three times available supply. Nvidia has locked in over 60% of that packaging capacity; Google had to cut its 2026 TPU production target from 4 million to 3 million units because it could not get enough. TSMC consumes 8–10% of Taiwan’s total electricity. It draws water from reservoirs in a region increasingly subject to drought. Its revenue is concentrated in two customers — Apple and Nvidia — that together account for more than half of its income. Samsung’s foundry share has fallen to 6.8%. Intel Foundry, despite $7.86 billion in CHIPS Act funding, has no major external customer. The semiconductor industry is tracking toward $1 trillion in annual sales, and the physical layer underneath that entire market — the fabs, the packaging lines, the interposers — runs through a 36,000-square-kilometre island 130 kilometres from mainland China. This is the single point of failure underneath every AI case in this library.
Of global foundry market. Over 90% of chips below 7nm. Q3 2025 revenue: $23.5B. Samsung foundry fell to 6.8%, down from 9.3% YoY.[1]
Planned capital expenditure. Up from $40.9B in 2025. Creates massive operating leverage: if demand normalises, fixed costs remain.[2]
Projected wafers per month by end of 2026, up from 35K in late 2024. Still oversubscribed. Demand 3× supply. The actual AI bottleneck.[5]
Apple + Nvidia account for majority of revenue. Any slowdown in either ecosystem cascades directly through TSMC’s financials.[3]
Of Taiwan’s total electricity. Water-intensive processes in a drought-prone region. Infrastructure dependencies compound geographic risk.[3]
Samsung: yield issues. Intel: no external customer, $7B annual foundry losses. No viable second source at leading edge for 2026–2028.[4]
The concentration is not a market failure. It is the logical outcome of TSMC’s foundry model, invented in 1987, which separated chip design from manufacturing and allowed fabless companies to innovate without building fabs. Over four decades, TSMC compounded its advantage: higher yields, more customers, more revenue, more investment, better technology, still higher yields. The virtuous cycle created a natural monopoly at the leading edge where the capital requirements — now exceeding $50 billion annually — represent an insurmountable barrier to entry.[1]
The at-risk thesis is not that TSMC will fail. It is that the global technology ecosystem has become structurally dependent on a single company whose most advanced operations are concentrated in a single geographic location subject to geopolitical risk, natural disaster risk, and infrastructure constraints. Warren Buffett reversed Berkshire Hathaway’s investment specifically because of this concentration. The risk is priced by some investors and ignored by most of the industry that has no alternative.[1]
Advanced packaging — specifically TSMC’s CoWoS (Chip-on-Wafer-on-Substrate) technology — has become the single tightest constraint in the global semiconductor supply chain. CoWoS bonds AI processors to high-bandwidth memory on a silicon interposer. Without it, the most advanced AI accelerators cannot be assembled. TSMC’s CEO confirmed supply remains oversubscribed, with demand running at approximately three times available capacity. The company is scaling from 35,000 wafers per month in late 2024 to a projected 130,000 by end of 2026 — and it is still not enough.[5]
Nvidia has secured over 60% of TSMC’s total CoWoS output for 2026. This capacity lock creates a structural moat: competitors do not just need a better chip design — they need access to the packaging line. Google cut its 2026 TPU production target by 25% specifically because of packaging constraints. AMD has secured approximately 11% of capacity. Everyone else fights for the remainder. Advanced packaging is now considered as technically demanding and capital-intensive as wafer fabrication itself.[6][7]
The pricing reflects the scarcity: advanced packaging prices are rising 10–20% annually, compared to 5% for logic wafers. Packaging revenue is approaching 9% of TSMC’s total, with margins near the company average. The back end of the semiconductor supply chain has become the front end of the AI economy.[8]
The geographic concentration of packaging is even more acute than fabrication. Almost all of TSMC’s advanced packaging remains in Taiwan, at facilities in Tainan and Chiayi. An Arizona packaging hub is planned for 2027 but does not yet exist. Amkor’s Arizona facility, intended to package wafers from TSMC’s Arizona fab, is not expected to begin operations until 2028. For at least the next two years, the physical assembly of virtually every advanced AI chip occurs on one island.[9]
| Dimension | Evidence |
|---|---|
| Operational (D6)Origin · 82 At Risk | TSMC’s operational infrastructure is the origin because the cascade flows from physical manufacturing concentration. ~70% foundry share, >90% of sub-7nm. CoWoS packaging sold out, demand 3× supply. $52–56B capex creating massive fixed-cost leverage. 8–10% of Taiwan’s electricity. Water-intensive processes in drought-prone region. Most advanced R&D stays in Taiwan despite Arizona/Japan/Germany diversification. AP7 and AP8 packaging facilities in Tainan and Chiayi are the physical chokepoint of the AI economy. No domestic US packaging until 2027–2028 at earliest. The operational dimension scores highest because every other dimension cascades from the physical reality of where chips are made and packaged.[1][5][9] |
| Regulatory / Geopolitical (D4)Origin · 80 At Risk | Taiwan Strait is the most geopolitically contested waterway on Earth. CHIPS Act ($52.7B) and EU Chips Act (€43B) are explicit policy responses to TSMC concentration risk. US government took 9.9% equity in Intel specifically to create an alternative. Export controls tightening: BIS added 65+ Chinese entities to Entity List in 2025. ASML DUV servicing in China remains unresolved. VEU status revoked for Samsung and SK Hynix China operations. The regulatory response confirms the systemic risk assessment: governments are spending over $100B collectively because they recognise that TSMC concentration is a national security vulnerability. The spending has not yet produced an alternative.[4][10] |
| Revenue / Financial (D3)L1 · 78 | TSMC 2025 revenue: $122B (+31% YoY). Q1 2026 guidance: $34.6–35.8B (38% growth). Gross margins 63–65%. Trading at ~24× forward earnings. Revenue concentrated in Apple + Nvidia. Any AI capex slowdown cascades immediately. The $56B capex creates operating leverage risk in both directions: if demand normalises, TSMC faces massive underutilisation costs. If demand exceeds supply, the rest of the industry is supply-constrained. The semiconductor industry is tracking toward $1T in annual sales, with TSMC capturing a disproportionate share of the value. The financial dimension is L1 because it is the direct consequence of operational dominance.[2][3] |
| Customer (D1)L1 · 75 | Every major AI company is a TSMC customer with no viable alternative at leading edge. Nvidia, Apple, AMD, Broadcom, Qualcomm, Google, Amazon, Microsoft — all dependent on TSMC for their most advanced chips. Google cut TPU production 25% due to CoWoS constraints. Apple rumoured to be exploring Intel 18A as a hedge. Custom ASIC designers (Broadcom, Marvell) entirely dependent on CoWoS allocation. The customer dimension captures the downstream impact: every company building AI infrastructure is exposed to TSMC availability, pricing, and allocation decisions. TSMC has become kingmaker — its packaging queue determines which AI companies can scale.[6][7] |
| Quality / Technology (D5)L1 · 72 | TSMC’s 2nm process is in risk production with GAA (gate-all-around) architecture, offering 70% efficiency gains over 3nm. CoWoS-L enables multi-die processors exceeding the reticle limit. SoIC provides bumpless 3D stacking at 6-micron bond pitch. The technology lead is widening, not narrowing. Samsung’s 2nm GAA yields reached ~60% in late 2025 but reliability concerns persist. Intel 18A yields estimated 55–75%. TSMC’s ecosystem of design tools (Open Innovation Platform) creates switching costs that make customer migration structurally difficult even if alternatives achieve parity on paper. The quality dimension is the moat that makes the concentration self-reinforcing.[3][4] |
| Employee / Talent (D2)L2 · 55 | TSMC employs approximately 76,000 people, predominantly in Taiwan. The company’s institutional knowledge of advanced manufacturing — from process engineering to yield optimisation — is concentrated in a workforce that operates in a single geography. Arizona fab ramp has been complicated by cultural and operational differences. TSMC’s competitive advantage is partly embodied in human capital that cannot be easily replicated or relocated. Intel’s foundry talent pool, while substantial, has not yet demonstrated the execution discipline that TSMC’s workforce delivers. The employee dimension is a second-order effect: if TSMC operations are disrupted, the human expertise to manufacture at leading edge does not exist elsewhere at the required scale. |
-- The Silicon Moat: 6D At-Risk Cascade
-- Semiconductor Cluster Case 1 of 4 (UC-103, UC-104, UC-105, UC-106)
FORAGE tsmc_concentration_risk
WHERE foundry_market_share > 0.65
AND advanced_node_share_sub_7nm > 0.90
AND cowos_demand_to_supply_ratio > 2.5
AND capex_annual > 50_000_000_000
AND customer_revenue_concentration_top_2 > 0.50
AND geographic_concentration = "taiwan"
AND alternative_foundry_viable = false
AND energy_share_of_national_grid > 0.08
ACROSS D6, D4, D3, D1, D5, D2
DEPTH 3
SURFACE silicon_moat
DIVE INTO concentration_cascade
WHEN single_source_leading_edge AND geopolitical_risk_elevated AND cowos_oversubscribed AND alternatives_failing
TRACE at_risk_cascade
EMIT at_risk_signal
DRIFT silicon_moat
METHODOLOGY 85 -- CHIPS Act $52.7B, EU Chips Act €43B, Intel 18A investment, Japan fab subsidies, Samsung 2nm push, geographic diversification attempts
PERFORMANCE 35 -- Intel no external customer, Samsung 6.8% share, Arizona fab not at leading edge, packaging still 100% Taiwan, TSMC share growing not shrinking
FETCH silicon_moat
THRESHOLD 1000
ON EXECUTE CHIRP at_risk "TSMC ~70% foundry, >90% sub-7nm. $56B capex. CoWoS sold out, demand 3x supply. Nvidia 60%+ of packaging capacity. Google cut TPU production 25%. Samsung 6.8% and falling. Intel 18A has no major external customer. $7.86B CHIPS Act has not produced alternative. Two customers = majority of revenue. 8-10% of Taiwan electricity. Advanced packaging 100% Taiwan until 2027-2028. $100B+ in government investment across CHIPS/EU/Japan has not changed the structural dependency. The silicon moat is the physical layer underneath every AI case in the library."
SURFACE analysis AS jsonRuntime: @stratiqx/cal-runtime · Spec: cal.cormorantforaging.dev · DOI: 10.5281/zenodo.18905193
The global response to TSMC concentration risk has been historically unprecedented in scale and historically predictable in result. The CHIPS and Science Act committed $52.7 billion. The EU Chips Act committed €43 billion. Japan subsidised TSMC’s Kumamoto fab. The US government took a direct 9.9% equity stake in Intel. The total investment exceeds $100 billion. The structural dependency has not changed.[4][10]
Intel’s 18A process — the centrepiece of the Western reshoring thesis — is now in production for Intel’s own Panther Lake CPUs. Technically, it represents Intel’s first use of gate-all-around transistors and backside power delivery. Commercially, it remains unproven: Broadcom cancelled its 18A orders after yields did not meet expectations. Nvidia halted testing. Intel’s foundry segment has posted multi-billion-dollar annual losses. CEO Lip-Bu Tan has ended the era of building capacity before securing customers. The Ohio megafab has been delayed to 2030. For Intel 14A, customers must commit before Intel ramps production. As of March 2026, no anchor customer has committed.[4][11]
TSMC’s own diversification efforts are real but limited. The Arizona fab (Fab 21) is operational for 4nm production, but the company has stated that the most advanced research and production will remain in Taiwan. The Japan Kumamoto fab serves mature nodes. The planned Germany fab focuses on automotive chips. None of these facilities replicate TSMC’s leading-edge capability. The advanced packaging that is the actual bottleneck — CoWoS, SoIC — remains entirely in Taiwan, with an Arizona packaging hub not expected until 2027 at the earliest.[1][9]
TSMC’s dominance is not the result of a single advantage but of a compounding cycle: scale produces better yields, which attracts more customers, which funds more investment, which widens the technology gap. Breaking this cycle requires not just matching TSMC’s current capability but outrunning a company that is spending $56 billion per year to stay ahead. Intel and Samsung are not catching up. They are falling further behind.
The industry narrative has focused on process node competition — 3nm versus 2nm, TSMC versus Intel 18A. The actual bottleneck is advanced packaging. CoWoS capacity determines which AI chips can ship, at what volume, on what timeline. Google cut TPU production by 25% because of packaging, not fabrication. The company that controls the packaging queue controls the AI hardware market. That company is TSMC.
The CHIPS Act, EU Chips Act, and allied subsidies represent the largest peacetime industrial policy investment in semiconductor history. The spending has correctly identified the problem and funded credible attempts at diversification. But semiconductor manufacturing advantage compounds over decades, not budget cycles. The money has bought time and optionality. It has not yet bought an alternative.
UC-103 is the substrate underneath the case library. UC-065 (The Treadmill) documents AI infrastructure spending — that spending flows through TSMC. UC-073 (Samsung strike) documents the fragility of the only alternative. UC-092 (Europe’s missing fabs) documents the continental gap. UC-100 (China) documents the adversary building a parallel stack. The silicon moat connects them all. Every AI case runs on chips that run through one island.
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